| 摘要 |
The circuit arrangement according to the invention and consisting of a number of flip-flops, gates and an up/down counter has the effect that when a clock signal to be received is missing, there is no control of a voltage-controlled oscillator. For this purpose, a control process is not immediately initiated when the phase of the locally generated clock is leading, but first only the delay time is measured. For the time measurement, the said counter is counted up and when the received clock signal appears, it is counted down. The result is that the control time for slowing down the generated frequency corresponds exactly to the previously measured delay time.
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