发明名称 DIGITAL SIGNAL REPRODUCTION CIRCUIT
摘要 PURPOSE:To attain adjustment for the amplitude characteristic, and the phase characteristic of a signal independently, and to easily extract good data, by providing waveform equalizers in a data system, and a clock system respectively. CONSTITUTION:A transmitted digital signal is supplied to a first binary circuit 4a through a first waveform equalizer 3a, and also, the correction of the amplitude characteristic is applied at the first waveform equalizer, and the digital signal is supplied to a second binary circuit 4b through a second waveform equalizer 3b, and the correction of the phase characteridtic is applied at the second waveform equalizer. The clock signal is formed at a PLL6 by using the signal from the second binary circuit, and the sampling of the signal from the first binary circuit is performed by the clock signal. In this way, it is enough that only the adjustment of the amplitude characteristic is performed in the data system, and that of the phase characteristic is performed in the clock system, thereby, it is possible to easily perform the optimum adjustment, and to obtain the extraction of the good data.
申请公布号 JPS6331339(A) 申请公布日期 1988.02.10
申请号 JP19860175240 申请日期 1986.07.25
申请人 SONY CORP 发明人 SENBA TETSUO
分类号 H04B3/04;G11B20/14;H04L7/02;H04L7/033;H04L25/02;H04L25/03;H04L25/40 主分类号 H04B3/04
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