| 摘要 |
A digital phase locked loop circuit for reading input data transmitted from storage media. Counter and adder components establish the time of arrival of input data bits. Inspection windows are established having durations and start/stop times that can be adjusted by correction signals so that subsequent data bits will be received in the middle of the inspection windows. Correction signals to the counter and adder components compensate for variations in the phase and frequency of input data transmitted from storage media. |
