发明名称 SAMPLING AND HOLDING CIRCUIT
摘要 PURPOSE:To reduce a noise component by using transistor (TR) provided reducing the jump of sampling pulses to a signal line, as sampling and compensating TR privided with shield gate. CONSTITUTION:If a DC-biased shielding gate 6 is connected adjacently to a phiSH gate 1, electrostatic coupling capacity C35 between the phiSH gate and the source part 3 and electrostatic coupling capacity CD5 between the phiSH gate and the drain part do not exist and the electrostatic coupling capacity between the phiSH gate and the signal line is only the electrostatic capacity CG5 between the phiSH gate and a channel area under the gate. Namely, a noise component inputted to a node 1' by the phiSH pulse is smaller than the variation of the potential V1 of the node 1' and the absolute value of the noise component is reduced. Thus, a noise component jumped into a signal and a component compensating the noise component can be reduced by using a MOS TR provided with the shielding gate, so that the noise component due to the variance of the transistor size of TRs Tr5, Tr6 can be reduced.
申请公布号 JPS59207092(A) 申请公布日期 1984.11.24
申请号 JP19830081215 申请日期 1983.05.10
申请人 NIPPON DENKI KK 发明人 MIWATA KAZUO
分类号 G11C27/02;(IPC1-7):G11C27/02 主分类号 G11C27/02
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