发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To reduce a pull-in time, and to stably generate a self-advancing output, by connecting two pairs of phase locked loops in series, and adding an output from a phase comparator in the phase locked loop at a front stage, on a low-pass filter in the phase locked loop at a rear stage through a gain apparatus. CONSTITUTION:The two pairs of the phase locked loops 1 and 2 are connected in series, and the output from the phase comparator 5 at the front stage, is added on the low-pass filter 10 at the rear stage through the gain apparatus 14. Since the pull-in time is decided corresponding to the time constant of the low-pass filter 10 at the rear stage when an input signal exists, it is possible to obtain a desired pull-in time by setting the time constant at a desired value. Also, when no input signal exists, the output signal of a phase locked loop circuit depends on a voltage controlled oscillator 7 at the front stage. So that the output of the voltage controlled oscillator 7 at the front stage holds a state before the input signal disappears, for a long time, and self-advances, by setting the time constant of the low-pass filter at the front stage at a larger value, a stable output signal can be obtained.
申请公布号 JPS6331314(A) 申请公布日期 1988.02.10
申请号 JP19860175150 申请日期 1986.07.25
申请人 TOSHIBA CORP 发明人 YAMAZAKI SHOICHIRO
分类号 H03L7/107;H03L7/07;H03L7/10;H03L7/14;H04L7/033 主分类号 H03L7/107
代理机构 代理人
主权项
地址