| 摘要 |
PURPOSE:To simplify interface to a main memory device, and to shorten the execution time of the interface, by putting the load/store operation instruction of a vector data on the same signal line as that of the load/store operation instruction of a scalar data, and controlling it by a buffer control circuit unitarily. CONSTITUTION:When a vector store operation designating command is sent from a command register 11 to the buffer control circuit 4 through a signal line 101, a command received at a command register 41 is decoded by a decoding circuit 43. When it is decided that the command is the store operation designating command of the vector data of such type that performs access to a buffer memory circuit 5, from a decoded result, a vector store data is sent from a vector arithmetic circuit 2 to the buffer control circuit 4 through a signal line 109. The instruction of the load/store of the vector data is put on the same signal line as that of the load/store operation instruction, and it is controlled by the buffer control circuit 4 unitarily. |
