| 摘要 |
PURPOSE:To attain DMA transfer between memories without sharply deteriorating the response of a CPU by counting the number of times of continuous DMA transfer, and when the count value coincides with a previously set up value enabling continuous DMA transfer, interrupting a DMA cycle and actuating the CPU. CONSTITUTION:When the count value 22 of a counter 15 coincides with the number 23 of continuous transfer data set up in a data number register 12, a coincidence signal 18 from a comparator 16 is activated, the output of an AND gate 25 is deactivated and a DMA control circuit 14 transfers its but using right to the CPU to activate CPU cycles 102, 104.... When the bus using right is transferred to the CPU and a DMA enabling signal 20 is deactivated, the contents of the counter 15 are cleared, a DMA request signal 19-1' is activated again and DMA is restarted. When the contents of a data counter register 11 are turned to zero, the bus using right is transferred to the CPU after the end of a DMA cycle 106 and a CPU cycle 107 is started. |
