| 摘要 |
PURPOSE:To use both even and odd numbers while combining both numbers as a selecting address by providing the titled circuit with a 2n-bit length data bus, a data switching circuit and a circuit for forming a data write strobing signal (WR) to an n-bit data length device and a read request signal (RD). CONSTITUTION:Since a control circuit 4 executes 8-bit data access to the device 1 twice instead of a CPU 2, a wait circuit 5 has to output a wait request to the CPU 2, and even if a wait request 16 is not outputted from the device 1, outputs a wait request 18 to the CPU 2. When the wait request 16 from the device 1 is generated, the wait request 16 is converted into the wait request 18 to the CPU 2. In order to inform the generation of the wait request 16 also to the control circuit 4, a wait signal 17 is generated. Consequently, the control circuit 4 can wait two accesses to the device 1 by using the signal 17. |
