| 摘要 |
PURPOSE:To contrive improvement of integrity, by decoding higher and lower bits of input signals with NAND circuits and by performing decoding of input signal patterns by selecting either the enhancement type MOS or depression type MOS. CONSTITUTION:This decoder is configured in such ways that the higher and lower four bits of an input signal of eight bits are decoded into inversion signals and non- inversion signals by one bit decoders 301 and 401, and transistor groups 302 and 402 composed of enhancement type MOSs E and depression type MOSs D are selectively turned on by the decoded signals. Therefore, the signal Hi which is the output of higher decoders 30 is input into the gate of a transistor 405 of lower decoders 40 after the logic ''0'' of an output line 304 is activated into a logic ''1'' by an invertor 306, and a decode signal Sj is obtained by activating the logic ''0'' of another output line 404 obtained together with the ON condition of the transistor group 402 into a logic ''1'' through another invertor 407. |
