| 摘要 |
PURPOSE: To enable an internal logic element to be supplied with power with minimal surge, by laying out N-channel MOS transistors whose drain is connected to a supply connection and whose gate and source are grounded, along the periphery of a semiconductor substrate. CONSTITUTION: N-channel MOS transistors 10 whose gate and source are grounded are laid out along a supply connection 1, Therefore, a greater number of transistors can be provided in comparison with prior arts. As a result, the N-channel MOS transistors with the grounded gate and souce having a very large width can be provided in the small gap between the peripheral section including the supply connection 1 and an internal logic element 4. Positive surge from the exterior can be pinched off by the MOS transistors and negative surge can be attenuated by the supply connection 1 as a diode. Thus, the internal logic element 4 can be supplied with stable power. |
