| 摘要 |
<p>An AND gate (40) includes first and second input leads (42,43) and an output lead (44). The AND gate (40) includes a first N channel MOS ("NMOS") transistor (58) which couples the output lead (44) to ground in response to the signal (IN1) on the first input lead (42) and a second NMOS transistor (60) which couples the output lead (44) to ground in response to the signal (IN2) on the second input lead (43). A buffer (76) having a high output impedance is coupled to the output lead (44) and tends to maintain the output lead (44) in a constant state. When the signal on the first input lead (42) goes high, the first NMOS transistor (58) turns off and a PMOS transistor (64) turns on, thereby coupling the output lead (44) to a high voltage source (VH) for a predetermined time period. If the second NMOS transistor (60) is off, the resulting pulse causes the AND gate output signal (Vout) to go high. The high impedance buffer (76) maintains the output lead (44) in the high state.</p> |
