| 摘要 |
PURPOSE:To obtain a device characterized by high latch-up resistance, an excellent frequency response characteristic and less dispersion in element characteristics, by forming a P-well, whose bottom surface is in contact with a substrate, on an epitaxial layer, which is formed on an N-type single crystal substrate having low resistivity, and forming MOS transistors on the P-well and the epitaxial layer other than the P-well. CONSTITUTION:An epitaxial layer 20, which has a thickness of 3-15 mum and includes N-type impurities of 1X10<14>-5X10<15>/cm<3>, is formed on an N-type silicon single crystal substrate 10, whose resistivity is lower than 0.1OMEGA-cm. A P-well 30, whose bottom surface is in contact with said N-type silicon single crystal substrate 10, is formed in the epitaxial layer 20. An N-channel MOS transistor is formed on said P-well. A P-channel MOS transistor is formed on the epitaxial layer 20, where the P-well is not formed. Thus, a C-MOS integrated circuit, which is characterized by a low threshold voltage, an excellent frequency response characteristic, less dispersion in element characteristics and improved latch-up resistance and can be used in an environment, wherein electric noises are severe, can be obtained. |
