发明名称 |
ARITHMETIC PROCESSOR |
摘要 |
PURPOSE:To attain the easy package of an arithmetic processor into an LSI by using a combination circuit containing the array of a small number of elements to form the arithmetic processor in order to minimize the transmission of the carry value and also to simplify a circuit constitution. CONSTITUTION:The basic arithmetic circuit of a single digit addition/subtraction forming an arithmetic processor uses the value of a control signal (q) to perform addition/subtraction. In other words, the part equivalent to the digit of the calculation expressed by an equation Z=X+Q(Y) is carried out by the basic arithmetic circuit. Here the X of a 1st member shows a redundant binary number and the Y of a 2nd member shows a redundant binary number containing non-negative digits excepting for the highest-order digit. Thus Q(Y)=Y and Q(Y)=-Y are satisfied with q=0 and q=1 respectively. Furthermore the addition is carried out for redundant binary numbers with q=0 and the subtraction is carried out between X and Y with q=1 respectively. Thus these operations are carried out by a same circuit. |
申请公布号 |
JPS6325728(A) |
申请公布日期 |
1988.02.03 |
申请号 |
JP19860170004 |
申请日期 |
1986.07.18 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
TAKAGI TADASHI;NISHIYAMA TAMOTSU;KUNINOBU SHIGERO |
分类号 |
G06F7/501;G06F7/49;G06F7/494;G06F7/503;G06F7/508;G06F7/52 |
主分类号 |
G06F7/501 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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