发明名称 SUPPRESSING SYSTEM FOR COMPLEXITY IN PACKET SWITCHING
摘要 <p>PURPOSE:To suppress an input to a packet switching set from a terminal, by adding a bit of information to represent a complicated state on a packet passing the packet switching set, when the packet switching set falls in the complicated state. CONSTITUTION:A complexity detecting part 1, and a suppression information adding part 2 are provided at a node, and a bit of suppression information is added on the packet in the reverse direction of the direction of communication in which the complicated state is generated at the node, then it is sent out. Since a logic link is not terminated, and a bit of information is added on a communication packet using the logic link, it is possible to send rapidly the bit of suppression information due to the complexity generated on the midvay of the logic link, to a terminating part. Also, by utilizing the fact that a transmission confirmation packet is transferred in the reverse direction of the direction of the communication along a communication logic link, the transmission confirmation packet of a junction line in the reverse direction corresponding to the junction line in the complicated, state can be captured. In this way, it is possible to inform the bit of suppression information due to the generation of the complexity automatically, to all of the equipments on a traffic generating terminal side performing the communication via a complicated junction line.</p>
申请公布号 JPS6324742(A) 申请公布日期 1988.02.02
申请号 JP19860168460 申请日期 1986.07.17
申请人 FUJITSU LTD 发明人 OGASAWARA KOJI;TSUTSUI HIDEKAZU;SAKAKAWA KAZUO;HASEBE TAKAYUKI
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