发明名称 |
Dynamic RAM refresh circuit |
摘要 |
A dynamic RAM refresh circuit provides the interface for timely refresh of up to 64K of RAM memory while simultaneously providing for minimal disruption of a CPU's access of that RAM memory. Circuitry is also provided to permit interlock control for timeshared access of the RAM memory on a shared basis with the refresh circuit.
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申请公布号 |
US4723204(A) |
申请公布日期 |
1988.02.02 |
申请号 |
US19850750658 |
申请日期 |
1985.07.01 |
申请人 |
GTE AUTOMATIC ELECTRIC INCORPORATED |
发明人 |
KHERA, MUHAMMAD I. |
分类号 |
G06F13/16;G11C11/406;(IPC1-7):G06F13/00;G11C13/00 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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