发明名称 I/O ADDRESS DECODING SYSTEM
摘要 PURPOSE:To connect many I/O devices to the same address in an I/O address space by providing a means for setting an intrinsic address of a hardware, and a means for selecting dynamically its intrinsic address by a software. CONSTITUTION:An intrinsic address decoding circuit 10 decodes an address of an I/O device which has been allocated to the prescribed I/O address space. In order to overlap and allocate plural I/O devices to its same I/O address spaces, a hardware intrinsic address setting part 12 is provided. To the setting part 12, a value for discriminating the I/O device which has been allocated to its overlapped address is set at the time of installing the I/O device. In case of selecting the I/O device to be used, the value held by the setting part 12 is written in a software use register 11 through a data bus 16 before sending out an address in its I/O address space. Thereafter, an access is executed to its I/O device, and by an output of an AND circuit 14, an access can be executed to a desired I/O device.
申请公布号 JPS6324343(A) 申请公布日期 1988.02.01
申请号 JP19860166981 申请日期 1986.07.16
申请人 FUJITSU LTD 发明人 MORIMOTO TERU
分类号 G06F13/14;G06F12/06 主分类号 G06F13/14
代理机构 代理人
主权项
地址