| 摘要 |
PURPOSE:To fetch contents from a main storage device and to continue high- speed action as a system even if parity errors or 2-bit errors in an ECC (error correction code) system occur in a data array by providing a group of registers which makes the main storage device continue accesses in case of detecting errors. CONSTITUTION:A cache memory which is controlled with a pipeline has an address back-up register 10a provided in parallel with an address register 10 where the physical address of data issuing errors is made to shelter, a data array address back-up register 9a provided in parallel with a data array address register 9 where the data address of the data issuing errors is made to shelter, a back-up register provided in a system controller 34 and a group of registers which makes the main storage device 12 continue the accesses even if errors are detected. Thus the system controller 34 accesses the data from the main storage device 12, so that a preceding request interrupted by the error can be executed to operate. |
