| 摘要 |
PURPOSE:To reduce the synchronous locking time by providing plural synchronizing pulse train pattern detection circuits. CONSTITUTION:When any of pattern detection circuits 21, 22-2p detects a pattern, a pattern detection signal S1 is fed to a clock blocking circuit 4 via an OR circuit 3, the gate closing is released to input a clock pulse to a frame counter 5. In receiving the pulse, the frame counter 5 gives a synchronous detecting trigger S2 to pattern detection circuits 21, 22,-2P after m-bit to command the pattern collation. Since the frame counter 5 is an m-bit counter, an output being the frequency division of the input pulse by 1/m appears and the result is frequency-divided further into 1/r by a multi-frame counter 6. On the other hand, a pattern sequencing circuit 7 receiving the output of the pattern detection circuits 21, 22-2p detects which synchronizing pulse train pattern is to be collated and the result is loaded to the multi-frame counter 6, which receives it and sends a frame phase signal S3 to the reception section. |
