发明名称 SUPERVISOR/RESETTING CIRCUIT FOR CPU
摘要 PURPOSE:To raise the stand-by time rate of a CPU, and to decrease the current consumption by always monitoring the stand-by time rate of the CPU, and applying the reset or interruption to the CPU, when this stand-by time rate has exceeded a prescribed range. CONSTITUTION:A supervisor/resetting circuit 6 always monitors the time rate of a HALT signal of a CPU 7, and when the time rate of the HALT signal exceeds a prescribed range which has been determined in advance, it is regarded as an abnormal state, and an ALM signal is outputted to the CPU 7. This circuit is constituted of an AND gate 12 so that AND of the ALM signal and a power-on reset signal (PS RESET signal) at the time when a power source has been turned on is inputted. In this way, when the ALM signal becomes active, the reset is applied to the CPU 7.
申请公布号 JPS6320548(A) 申请公布日期 1988.01.28
申请号 JP19860165341 申请日期 1986.07.14
申请人 NEC CORP 发明人 MAEDA KOJI
分类号 G06F11/30;G06F11/00 主分类号 G06F11/30
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