| 摘要 |
<p>A multiplexer includes first and second frequency dividers (101,102) and first and second selectors (103,104). The first frequency divider (101) receives a clock signal which determines a multiplexing time slot and outputs a first signal every M (M >/= 2) time slots. The second frequency divider (102) receives the first signal from said first frequency divider (101) and outputs N (N >/= 1) second signals having different phases. The first selector (103) converts N insertion codes such as a frame synchronization code and a service code into one code signal train on the basis of the second signals. The second selector (104) receives a digital data signal train having an alternate repetition of a digital data signal using (M - 1) continuous time slots and a gap of one time slot and inserts the insertion codes of the code signal train on the basis of the first signal.</p> |
