发明名称 METHOD OF DETECTING & HANDLING MEMORY-MAPPED I/O BY PIPELINED MICROPROCESSOR
摘要 A method for detecting and handling memory-mapped I/O in a pipelined data processing system is provided. The method uses two signals on the system interface: when the system generates a read bus cycle, it activates an output signal if certain I/O requirements are not satisfied; an input signal is activated when the reference is to a peripheral device that exhibits certain characteristics; when the system detects that both the input signal and the output signal are active, it discards the data read during the bus cycle, serializes instruction execution and regenerates the read bus cycle, this time satisfying the requirements for I/O such that the output signal is driven inactive.
申请公布号 GB8729327(D0) 申请公布日期 1988.01.27
申请号 GB19870029327 申请日期 1987.12.16
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人
分类号 G06F9/38;G06F13/14 主分类号 G06F9/38
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