Multi-channel shared resource processor.

摘要

An external dispatcher distributes prioritize tasks to a plurality of processor channels. The processor channels then contend for one of two partitions for the execution of instructions assigned thereto during a multiphase instruction cycle. Two unique processor channels, working on unrelated tasks, utilize the even and the odd partitions to execute a single instruction assigned to the respective processor channels. The instruction cycle is subdivided into phases in order to maximize the use of a memory system and the CPU. When one of the partitions is accessing the memory system and working registers associated therewith, the other partition is utilizing the CPU. The net result is the efficient use of all memory bandwidth and the CPU without requiring pipe lined set/execute structures common on high performance micro-program systems.