| 摘要 |
The damping device has at least one register (REG 1) on its input side, and a further register (REG 2) on its output side. It incorporates a segment convertor (0m1), and a further convertor (Om2) for stages within the segment 0. Two changeover switches (P1,P2) by-pass and couple the respective convertors in close contact between the registers. The device works with two function positions: damping and non-damping. These positions are determined by means of a signal (ATT) which controls the changeover switches (P1,P2). The PCM signal to be damped is recorded in the first register (REG 1), and the damped such signal is read out from the second register with a time slot delay. In a further formation, a third register is arranged in parallel with the first, and a three -bit count-down unit is used to contribute to a simplified structure involving a low number of grids in the logic network. |
