| 摘要 |
PURPOSE:To correct a steady-state phase error of a PLL circuit with less circuit scale by generating a control voltage for frequency locking and a control voltage for correcting steady-state phase error superimposingly on an input of a loop filter. CONSTITUTION:An NAND circuit 10 inputs an input clock signal (a) and a signal through NOT circuits 7-9 of the signal (a), generates a pulse (b) being a difference of amount of delay of the circuits 7-8 to set an FF 11 and a signal (d) is outputted from the FF11 at the trailing edge of an output clock signal (c). Further the signals (c) and (a) are ORed 12 exclusively, a signal (e) inverting 13 the result, signals (d) and e', signals d' and e', and signals d' and (e) are inputted to NAND circuirs 14-17, a constant current is fed to outputs signals f-i from a constant current circuit 20 through resistors R1-R4 to obtain a signal (j). The signal (j) is the superimposition of the control voltage for frequency locking and the control voltage for steady-state phase error correction, this voltage is averaged by a loop filter 2 and applied to a voltage controlled oscillator 3 to correct phase error. |
