| 摘要 |
A memory address generator has an encoding circuit with an encoding function, in which the maximum encodable quantity is given by n1 words . m1 rows (the address in the position of the nth word . the mth row being given by n1 . m+n), and an address extension circuit to convert the addresses which are generated by the encoding circuit into addresses (addresses in the position of the nth word . the mth row are given by n2 . m+n) in an area of n2 words . m2 rows (where, at least, n2 > n1 or m2 > m1) of a bit plan memory. <IMAGE>
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