Method and arrangement for control of access to the memory system consisting of cache memory and working memory in a data processing system

摘要

Starting from the fact that, for accesses to the memory system with cache memory (CACHE), data are available and can be modified at the earliest within an initiated memory work cycle when the HIT-MISS controller (H/M) supplies its result signals (H0, H1), access requests lead to the initiation of a memory work cycle even if tests for the legality of the access are not yet concluded. These tests are concurrent with the start of the memory work cycle, so that no time loss occurs in the normal case. If the initiated access cannot be carried out or has to be postponed, the memory work cycle which has already been initiated is simply broken off, which is achieved by a monitoring circuit (K-S) which is connected to the cache memory controller (CA-ST). <IMAGE>