| 摘要 |
<p>PURPOSE:To reduce a cycle period by providing a timing generator generating all internal control signals in response to either leading or trailing of a clock pulse. CONSTITUTION:The timing generator 1 generates internal control signals 12, 13, 14 relating to functions A, B, C in response to the front edge FE of a clock pulse P1 and generates the internal control signal relating to a function C after the realization of the function B is finished. After the end of relizing the function C, internal control signals 16, 17, 18 relating to functions E, G, H are generated and an internal control signal 19 is generated relating to a function F after the end of realizing a function E. Thus, signals 12-19 are generated based on the front edge FE of the pulse P1, the entire cycle period is utilized without needing the pulse P1 into the high level and low level periods to attain high speed. Further, the input voltage level is processed by one conversion only and the delay time is reduced. Further, the similar processing is applied also as to the rear edge.</p> |
