发明名称 CLOCK PHASE LOCKING SYSTEM
摘要 PURPOSE:To perform the phase locking of a system clock with high accuracy by driving an A/D converter with a clock pule and digitizing the input picture signal applied with the dot interlace. CONSTITUTION:The digital signal obtained by applying an A/D conversion 1 to the input picture signal applied with the dot interlace is transmitted to a frame pulse detecting circuit 2 and a horizontal synchronizing gate 3 to detect the frame and a horizontal synchronizing pulse. An internal horizontal synchronizing pulse applied with the phase control by said detected synchronizing pulse is produced by a synchronizing pulse generator 5. Then a phase detector 6 detects the phase difference between the horizontal and internal horizontal synchronizing pulses. A voltage control oscillator 9 produces a clock pulse applied with the phase control in response to the phase difference detected by the detector 6. The A/D converter 1 is driven by the clock pulse of the oscillator 9. Thus the input picture signal whose clock pulse is locked in phase and applied with dot interlace is digitized.
申请公布号 JPS59221091(A) 申请公布日期 1984.12.12
申请号 JP19830093359 申请日期 1983.05.28
申请人 NIPPON HOSO KYOKAI 发明人 NINOMIYA YUUICHI;OOTSUKA YOSHIMICHI
分类号 H04N5/04;H04N7/56 主分类号 H04N5/04
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