发明名称 ADDING AND SUBTRACTING DEVICE
摘要 PURPOSE:To process a digital signal at a real time at a high speed by providing a means to determine the number of the bit necessary to a shifting in accordance with the adding result and the data of the difference of the index displaying part of respective data. CONSTITUTION:An output gamma of a latch circuit 71 is inputted tone side input terminal of a constant adding circuit 77 and a subtracting circuit 78. A zero detecting circuit 79 to decide an output UM of an adder 75, when the output UM of an adder given by a complement displaying is a positive number, counts the continuous number of the '0' bit continuous to the sign bit at the upper-most order of the output UM. When the output UM is a negative number, the continuous number of the '1' bit continuous to the sign bit is counted. An output theta1 of the zero detecting circuit 79 is given through an output correcting circuit 80 provided for the regularization of the data and the overflowing countermeasure to a shifting circuit 76 and the number of the shifting bit of the data by the shifting circuit is determined. Thus, the digital signal can be processed at a high speed.
申请公布号 JPS6312025(A) 申请公布日期 1988.01.19
申请号 JP19870024590 申请日期 1987.02.06
申请人 HITACHI LTD;HITACHI DENSHI LTD 发明人 HAGIWARA YOSHIMUNE;SUGIYAMA SHIZUO;MAEDA SHIGEMICHI;YUMOTO OSAMU;AKAZAWA TAKASHI;KOBAYASHI MASAHITO;KITA YASUHIRO;KIDA YUZO
分类号 G06F7/485;G06F7/00;G06F7/50;G06F7/508;G06F7/527;G06F7/76;G06F17/10 主分类号 G06F7/485
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