发明名称 DEFECT INFORMATION COLLECTING SYSTEM
摘要 PURPOSE:To collect the information of a memory element in a logical device at a high speed by providing an initial value setting instruction from a diagnosing control device to an address register, an address updating instruction and a contents reading bus of a reading register. CONSTITUTION:When the contents of a memory element 4 are to be read at the time of the defect, a diagnosing control device 3 supplies a changing-over signal to a changing-over part 22 and the initial address value supplied to a memory element 4 is set through an initial value setting instructing signal line 200 to a register 20. The register 20 supplies the address data to be latched through the changing-over part 22 to a memory element. For the address data latched to the register 20, an adder 5 is operated by an updating instruction signal supplied from the diagnosing control device 3 through an address updating instruction signal line 202, the data corresponding to the adding address are supplied to a register 21 with a constant value at a constant part 23, the register 21 latches this value and supplies it through a reading bus 201 to the diagnosing control device 3. Thus, the memory element information can be collected at a high speed.
申请公布号 JPS6312038(A) 申请公布日期 1988.01.19
申请号 JP19860156458 申请日期 1986.07.02
申请人 NEC CORP 发明人 TABATA KYOICHI
分类号 G06F11/22 主分类号 G06F11/22
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