发明名称 Solder finishing integrated circuit package leads
摘要 A new method for solder finishing the leads of an integrated circuit package such as a DIP having two parallel rows of leads along the sides of the package. The method contemplates establishing two vertical columns of falling molten solder and spacing the columns apart a distance substantially the width of the package. The package is passed between the vertical columns of falling molten solder immersing the two parallel rows of leads along the sides of the package in the respective columns of molten solder, washing the leads and depositing a finishing layer of solder over the surfaces of the leads. The method further contemplates directing hot nonreacting gas over the leads of the package as the package passes from the columns thereby eliminating excess solder and bridging of solder between the leads. A monorail track system and a new solder bridge for implementing the method are described. The invention may be applied for column fluxing as well as for other column liquid treatments.
申请公布号 US4720396(A) 申请公布日期 1988.01.19
申请号 US19860878307 申请日期 1986.06.25
申请人 FAIRCHILD SEMICONDUCTOR CORPORATION 发明人 WOOD, RICHARD C.
分类号 H01L23/50;B23K1/08;H01L21/48;H01R43/02;(IPC1-7):B05D5/12 主分类号 H01L23/50
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