发明名称 SIGNAL FAULT DETECTION SYSTEM IN BALANCED DOUBLE CURRENT INTERCHANGE
摘要 <p>PURPOSE:To detect a fault by detecting a duty difference signal when at least one line of balanced double current interchange lines connected to a balanced double current interchange circuit is faulty. CONSTITUTION:A reception signal (a) from the balanced double current interchange circuit 1 is a signal having a period T and retarded by a time (t) by a delay circuit section 2. Then a fault detection pulse (c) obtained from a gate 3 ANDing the reception signal (a) and a delay signal (b) retarded by the delay circuit section 2 is given to a signal fault detection circuit section 4, which detects whether or not the reception signal (a) is in error and gives an output a fault information signal (d). If either one of the balanced double current interchange lines 5a, 5b is opened, the received signal a' is retarded by a time (t) by the delay circuit section 2, outputted as a delay signal b', but a fault detection pulse c' ANDed by the reception signal a' and the delay signal b' is not outputted as a pulse, and the signal fault detection circuit 4 outputs the fault information signal (d) as a fault.</p>
申请公布号 JPS6310920(A) 申请公布日期 1988.01.18
申请号 JP19860154099 申请日期 1986.07.02
申请人 NEC MIYAGI LTD 发明人 HIRAIWA HIDEAKI
分类号 H04B3/46 主分类号 H04B3/46
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