| 摘要 |
PURPOSE:To shorten an image regenerating min. time to a large extent and to simultaneously realize faithful image regeneration and high speed image regeneration in an original image, by directly inputting a binary type multi-value image signal to a counter circuit of plural bits and obtaining pulse width modulation output corresponding to the image signal of each picture element. CONSTITUTION:In a shift mode, drive elements hold a clock signal 26 in common and operate as a first row shift register consisting of memory elements 31, 51 and a second row shift register consisting of memory elements 32, 52. The output terminal Q of each memory element outputs an image signal and is stable. In a count mode, the memory elements 31, 32 and the memory elements 51, 52 function as two-bit binary counters. Since the output Q of each memory element outputs an image signal at the time of the shift mode, the load pulse for setting the initial value of a counter circuit is unnecessary. The counter circuit is a decremental counter circuit and a driving control circuit detects a 'Low' level on the basis of all of counter output values and reverses the output pulses 43, 63 of the drive element and prohibits the input of the clock signal of a counter and pulse width modulation output corresponding to the image signal is obtained. |
