| 摘要 |
PURPOSE:To retry an instruction where malfunction occurs and improve reliability by holding a vector instruction which is not executed even when a scalar instruction and a vector instruction are processed in parallel for the high speed execution of the instructions. CONSTITUTION:Scalar instructions and vector instructions are set up previously in a main storage device together. An instruction reexecution pointer register 26 controls the address of an instruction to be retried even if malfunction occurs to the instruction processed by a pipeline while the scalar instructions and vector instruction coexit and are processed sequentially. Namely, while the scalar instructions and vector instructions are processed in parallel for high-speed processing, a readout address register 35 points unexecuted instructions in an instruction word stack 29 unless the operands of both instructions do not coincide with each other. Consequently, the instructions pointed by the circuit 35 are read out of the circuit 29 even in case of malfunction and supplied through a selecting circuit 30 to a vector instruction decoding part 31 to be reexecuted. |
