发明名称 CONTROL SYSTEM FOR INSTRUCTION RETRIAL
摘要 PURPOSE:To discriminate an intermittent fault from a fixed one and to prevent deterioration of the performance of an information processor containing an instruction retrial function, by clearing the history of success frequency in case this frequency does not reach a fixed level within a fixed time. CONSTITUTION:An instruction is retried by an instruction retry control circuit 1 when a logical device 12 has a fault and the number of times of retrial is counted by a counter 7. At the same time, the monitor of time is started. When an overflow detecting circuit 8 detects an overflow within a fixed time, a program instruction execution control circuit 3 inhibits the retrial of the subsequent instructions against the circuit 1. The contents of a timer register 4 are decreased at each fixed time interval and all-0 is detected. Then the circuit 3 decides an intermittent fault and erases the history of success frequency of the instruction retrials.
申请公布号 JPS6310243(A) 申请公布日期 1988.01.16
申请号 JP19860154898 申请日期 1986.07.01
申请人 NEC CORP 发明人 JITSUPOU AKIRA
分类号 G06F11/14 主分类号 G06F11/14
代理机构 代理人
主权项
地址