CLOCK SIGNAL SWITCHING CIRCUIT

摘要

PURPOSE:To prevent the pulse width at switching from being decreased by conducting selection/non-selection of a clock signal at clock signal changeover in synchronizing with the leading of this clock signal. CONSTITUTION:A logical value of an input to positive edge trigger type D flip- flops FF1, FF2 is sampled at the leading of a signal to a clock (CLK) input. When selection commanding signals SEL1, SEL2 commanding the selection of CLK1, 2 are respectively logical 1, 0 and output signals QFF1, 2 of the FF1, 2 are respectively logical 1, 0, the CLK1 is outputted to an output terminal OUT, and when the signal SEL1 changes from 1 to 0 and the signal SEL changes from 0 to 1, since an output of a gate G4 is 0, the signal QFF1 goes to 0 at the leading point of time of the next CLK1, an output of a gate G1 goes to 1 and the output is not outputted to the output terminal OUT. Further, when the signal QFF1 goes to 0, a gate G5 goes to 1, the signal QFF2 goes to 1 at the leading of the CLK immediately thereafter and the CLK2 is outputted to the output terminal OUT.