| 摘要 |
PURPOSE:To reduce the scale of the hardware of the titled circuit by providing an odd number of several line memories and switching the memories cyclically sequentially every time data are written in the unit of lines to one area of the line memories. CONSTITUTION:A data signal outputted from 1 delay means l by a prescribed time of delay is supplied in an odd number of several line memories 20 and an area in a storage means 2 by using a write signal and written in as the data by one line. When the write of data by one line is finished, the data signal is written in the next memory 20 and area designated by the write signal. Similarly, the data signal is written in each memory 20 and each area sequentially and cyclicly while the memories are being switched. Thus, in case of readout, all odd or even order number of data signals in the memory 20 are read simultaneously by using a read signal from a read means 4. Thus, the data are outputted in parallel to form 2-dimension data and the scale of hardware of the titled circuit is reduced. |
