| 摘要 |
<p>A transistor arrangement with a power transistor (T1, T2) which can be disconnected at a particularly high speed. For this, a discharging transistor (T4) is provided which, after the base current of the output transistor has been switched off, discharges the charge carriers from the base area of the output transistor. Behaviour is improved by a sequential transistor (T3), whose intrinsic storage capacity of charge carriers on the base is exploited. Furthermore a description is given of a diffusion structure particularly suited for monolithic integration.</p> |
