| 摘要 |
PURPOSE:To make automatic correction of an error possible and improve reliability of a computer system by emulating in a parity mode in ordinary time, and switching to an ECC mode and emulating when an error occurred in an adder-subtractor which is an object of emulation. CONSTITUTION:A predicting means 17 that changes to an error detecting and correcting ECC mode that predicts check bit data of output information from check bit data of input information when an error occurred at the time of emulation in a parity mode and a means 15 that detects the content of the error from predicted check bit data from the predicting means 17 and output data of addition and subtraction and corrects the error of output information are provided. When emulating multiplication and division by a shifter, an adder- subtractor etc., the predicting means 17 makes parity predicting operation in a parity mode by the adder-subtractor, and an error occurred when emulating in parity mode check bit prediction is made in an ECC mode and detected whether the content of the error is 1 bit error or 2-bit error, and 1 bit error is corrected automatically. |
