发明名称 |
ARITHMETIC PROCESSING UNIT |
摘要 |
PURPOSE:To contrive to perform the arithmetic processing at a high speed by providing a partial remainder determining part with a circuit which inverts the sign of an internal operand in accordance with the sign of each digit of an already determined quotient. CONSTITUTION:The partial remainder determining part consists of the first step operation provided with the first means 514 which determines intermediate carry (intermediate borrow) in addition (subtraction) between digit expression numbers with signs and the second means 513 which determines an intermediate sum (difference) of addition (subtraction) and the second step operation provided with the third means 515 which obtains the sum (difference) between the intermediate sum (intermediate difference) and the intermediate carry (intermediate borrow) from the just lower digit for each digit. The fourth means 511 which inverts the sign of the digit expression number with sign, which is the common input of the first means 514 and the second means 513, in accordance with the value of the control signal is added to execute addition and subtraction for division by only addition (subtraction) of digit expressions with signs. |
申请公布号 |
JPS638825(A) |
申请公布日期 |
1988.01.14 |
申请号 |
JP19860152452 |
申请日期 |
1986.06.27 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
NISHIYAMA TAMOTSU;KUNINOBU SHIGERO |
分类号 |
G06F7/537;G06F7/49;G06F7/506;G06F7/508;G06F7/52;G06F7/535 |
主分类号 |
G06F7/537 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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