发明名称 Noise reduction circuit.
摘要 <p>The present noise reduction circuit comprises a first circuit (20, 22) for extracting a relatively high frequency component of an input singal and amplitude-limiting a component of said amplitude-limited high frequency component exceeding a predetermined level, a second circuit (2l) for delaying said input singal such as a video signal by a predetermined time, and a third circuit (24) for adding outputs of said first and second circuits and outputting an added result as an output of said noise reduction circuit.</p>
申请公布号 EP0252763(A2) 申请公布日期 1988.01.13
申请号 EP19870306156 申请日期 1987.07.10
申请人 VICTOR COMPANY OF JAPAN, LIMITED 发明人 FUKUDA, HISATOSHI;FUJIHARA, HISASHIGE
分类号 H03H7/01;H04N5/21;H04N5/911 主分类号 H03H7/01
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