| 摘要 |
<p>A vertical field effect transistor (FET) (e.g., 20) disclosed which has a relatively short channel length and which reduces parasitic capacitance without employing a mesa isolation technique. A short channel length is achieved as a consequence of the fact that the source electrode (e.g., 56) of the FET is used as an etching and shadow mask to form two gate electrodes (e.g., 62), on the opposite sides of the source electrode, which are aligned with the sides of the source electrode. Parasitic capacitance is reduced because two of the contact pads (e.g., 82 and 84) of the FET are formed on a region of the semiconductor body (de.g., 24) of the FET whose electrical resistivity has been increased through the implantation of appropriately chosen ions.</p> |
