发明名称 MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To obtain the titled device which can realize the speed-up of design and the full display of the effect of multilayer wiring by a method wherein rectangularly intersecting double wiring layers are provided on the wiring region between each of macro cell arrays, and remaining wiring layers are made to obliquely intersect those. CONSTITUTION:Of terminals 21a-21d of the macro cell arrays 3, the terminals 21a and 21d are insulated and isolated from each other and then connected to the first layer wiring 22a rectangularly intersecting by means of the second layer wirings 23a and 23b. Besides, the terminals 21b and 21c obliquely intersect with the directions of the first layer wiring 22a and the second ones 23a, 23b, respectively, and then connected to the third layer wiring 24a rectangularly intersecting by means of the forth one 25a. In this construction, wirings are not superposed on each other in the direction of extension thereof and thus come into a clear state during designing. The superposition of through holes 26a, 26b, and 27a can be avoided without expanding the interval between the macro cell arrays 3, leading to difficulty in receiving the restriction of through hole arrangement. Thereby, high speed wiring design with an automatic wiring system, etc. can be realized, and the effect of multilayer wiring can be fully displayed.
申请公布号 JPS59220949(A) 申请公布日期 1984.12.12
申请号 JP19830096140 申请日期 1983.05.31
申请人 TOSHIBA KK 发明人 YOSHIDA SHIGEKI
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118;(IPC1-7):H01L21/82 主分类号 H01L21/822
代理机构 代理人
主权项
地址