Multi-level test probe assembly for IC chips

摘要

A multi-level test probe assembly for checking an integrated circuit chip before terminal leads are applied to the contact pads thereof which are deployed on the chip on a common plane, some pads being inwardly displaced relative to other pads. The assembly includes a planar insulation card provided with a port and having a printed circuit thereon whose traces are connected to a plurality of test terminals connectable to external testing equipment. Surrounding the port and bonded to the card is a mounting ring of dielectric material having a flat face on which is supported a first radial array of fine wires lying in a horizontal plane, the trailing end of each wire being connected to a respective trace. The wires cantilever across the port and converge toward the central region thereof below which is disposed the chip to be tested, the tapered leading end of each wire being double bent to define a needle having a shank section and a tip section terminating in a tip which engages a respective contact pad on the chip. Overlying the first layer and bonded thereto is a second layer of dielectric material having embedded therein a second radial array of fine wires whose tips engage those contact pads on the chip not engaged by the first array.