发明名称 MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To require no exchange operation of the ROMs of all slave processor modules by writing a program for an IPL in a memory circuit in the slave processor module from a master processor module. CONSTITUTION:A memory writing circuit 35 in the slave PUM30 operates through an instruction command transmission circuit 24 by a PU21 in the master processor module PUM20 at the time of the IPL and the program of a file device 40 is written to the memory circuit in the PUM30 according to a writing signal 37. Then, according to a reset instruction to the slave PUM30 from the circuit 24, a signal forming circuit 36 in the slave PUM30 operates and a PU31 is reset by a reset signal 38. Thereafter, the PU31 reads the program of the memory circuit 34, in the master PUM20, by a communication bus 10 between the PUMs via the file device 40, the PU21, a memory 22 and an interface 20 and by the interface 33, the PU31, the memory 32 of the slave PUM30, the IPL is performed.
申请公布号 JPS635463(A) 申请公布日期 1988.01.11
申请号 JP19860150361 申请日期 1986.06.25
申请人 NEC CORP 发明人 ISHIDO TEIICHI;MURATA TAIICHI
分类号 G06F9/445;G06F15/16;G06F15/177 主分类号 G06F9/445
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