| 摘要 |
PURPOSE:To improve the testing efficiency of carry by providing a carry forcing circuit supplying a carry signal forcibly to a required flip-flop circuit except the first stage circuit in response to the of the test mode. CONSTITUTION:The carry forcing circuit Fenfo is placed to carry signal lines S1, S2 between binary counters CUNT7, CUNT8 in order to connect/disconnect the carry signal lines S1, S2 on the way at the high and low-order electrically and N-channel transfer MOSFETs Qf1, Qf2 are interposed. A test signal phitest is fed to gates of the transfer MOSFETs Qf1, Qf2. With the test signal phitest at a low level, it instructs the test mode. Thus, in instructing the test mode, the carry signal liens S1, S2 are separated into the low-order bytes and the high-order btes from the midpoint electrically. Thus, a ripple counter circuit counts the low-order and the high-order bytes in parallel. |
