| 摘要 |
PURPOSE:To reduce gate leakage by forming an N-type GaAs layer supplying a channel with electrons onto a high-purity InP channel layer and shaping a gate electrode controlling the channel and a source electrode and a drain electrode brought into ohmic-contact with the channel. CONSTITUTION:A high-purity undoped InP layer 8 is grown on a semi-insulating InP substrate l in 5000Angstrom through a method such as a VPE method, an N-type GaAs layer 6 is grown in 500Angstrom in donor concentration of 5X10<17>cm<-3> through a method such as an MBE method, and an N<+> contact layer 9 is formed through a method such as an ion implantation method. Lastly, a gate electrode 3 and a source electrode 4 and a drain electrode 5 are shaped through a normal method, thus realizing an FET. Consequently, the large value of 4000-5000cm<2>/v.s is obtained at room temperature as the mobility of channel electrons, and the value corresponds to treble or quadruple as large as the mobility acquired by a conventional MISFET. Gate leakage currents are reduced and extremely excellent characteristics are obtained even in FET characteristics. |
