发明名称 ARITHMETIC LOGICAL OPERATION UNIT
摘要 PURPOSE:To increase an arithmetic speed by using a Josephson element to attain the circuit constitution making the best use of the fast operating properties of the Josephson element. CONSTITUTION:The Josephson elements are used to all circuit elements 16 and 18-53 to form the OR-AND circuit constitution applying the principle of duality. Furthermore the input signals A and B and the inverse of signals A and B of a circuit including a full adder 17 are used as relative signals together with control signals Cin, S0-S2 and the inverse of signals Cin and S0-S2. Thus the output signals of an OR circuit 18 and an AND circuit 16 are supplied to the majority circuits 52 and 53. Then the circuits 52 and 53 secure the majority logic of input signals and output them to the output terminals 55 and 54 as a carry signal C2 and the inverse of C2 to be applied to the next stage. While the signals obtained from OR circuits 46, 47, 49 and 50 and AND circuits 48 and 51 of the adder 17 are outputted to terminals 56 and 57 as the arithmetic output signals F1 and the inverse of F1.
申请公布号 JPS633332(A) 申请公布日期 1988.01.08
申请号 JP19860145893 申请日期 1986.06.20
申请人 FUJITSU LTD 发明人 KOTANI MASATAKE
分类号 G06F7/00 主分类号 G06F7/00
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