| 摘要 |
PURPOSE:To eliminate the need for the changeover by a switch or the like by switching a clock used for signal reception into a reception clock or a clock being the output of a DPLL circuit depending on the frame synchronization establishment state. CONSTITUTION:A frame synchronization circuit 2 uses A reception clock being the result of retarding a transmission clock (c) to sample a reception signal (a) and informs a display signal (d) to a clock switching control circuit 4 when the detected frame position synchronizes with a desired position being the result of a prescribed delay to the transmission frame. Thus, a clock switching control circuit 4 activates the reception section by using the timing of a fixed sampling system. If no synchronisation is established, a frame synchronization circuit 3 uses a clock (b) outputted from the DPLL circuit 1 to sample the reception signal (a) thereby establishing the frame synchronization and uses a display signal (e) to inform the synchronizing state to the clock switching control circuit 4. Thus, the rception section is operated by using the timing of the DPLL system. |
