发明名称 BIAS CURRENT COMPENSATING CIRCUIT
摘要 This circuit comprises a current source stage connectable to a capacitor which is controlled so as to alternately and periodically charge with the current fed by the source stage and discharge through a switch element, so as to generate a saw-tooth wave voltage. A buffer circuit, with low-impedance output is connected to the capacitor, for feeding a saw-tooth shaped low-impedance voltage signal to a load. In order to prevent the bias current of the buffer stage from introducing an error in the capacitor charge current and in the frequency of the saw-tooth voltage, a current sensor is provided connected between the buffer stage and the current source stage so as to vary the current generated by the source stage in an equal but opposite manner with respect to the error current due to the buffer stage.
申请公布号 JPS633509(A) 申请公布日期 1988.01.08
申请号 JP19870151033 申请日期 1987.06.17
申请人 SGS MICROELETTRONICA SPA 发明人 SHIRUBUAANO GORUNAACHI;ROBERUTO BUISUKARUDEI;SHIRUBUAANO KOTSUCHIETSUCHI
分类号 H03K4/50;H04N3/16 主分类号 H03K4/50
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